Fast simulation of VLSI interconnects

This work introduces an efficient and accurate interconnect simulation technique. A new formulation for typical VLSI interconnect structures is proposed which, in addition to providing a compact set of modeling equations, also offers a potential for exploiting sparsity at the simulation level. Simulations show that our approach can achieve 50 /spl times/ improvement in computation time and memory over INDUCTWISE (which in turn has been shown to be 400 /spl times/ faster than SPICE) while preserving simulation accuracy.