Implementation of a large scale hardware neural network system based on stochastic logic

We present a large scale hardware neural network system which consists of 16 chips, 1024 neurons. The system is realized by using stochastic logic. Stochastic logic makes possible to implement numerous neurons on a VLSI chip and to build a system comprising multiple chips easily. In addition, stochastic logic has a characteristic as some noise is generated while coding operations. This noise is effective for escaping from the local minima in a Hopfield network. The availability of this noise is confirmed in the measurement of our system.