Design and implementation of fast inverse modulo (2/sup 16/ +1) multiplier used in idea algorithm key schedule on FPGA

This paper presents new design and implementation for the inverse modulo (2
¹⁶
+1) multiplier to be used in the International Data Encryption Algorithm (IDEA) for key scheduling. The design is done using a novel realization of the power algorithm for Euler’s theorem, which results in the fast inverse modulo multiplier. IDEA key schedule modules are easily implemented, but the only overhead is introduced by the inverse modulo multiplier. The task of the inverse modulo multiplier circuit is to generate 18 inverses modulo multiplicative keys. The new design of the inverse modulo multiplier is based on squaring the output from the modulo multiplication operation then storing this output to use it again and this is done 14 successive times. Consequently, this new design results in fast inverse modulo multiplier realization, which calculates the inverse modulo multiplicative key in only 30 clocks rather than 65535 clocks using Euler's theorem only.