Suppression of erased state V/sub t/ drift in two-bit per cell SONOS memories

In this letter, we report on the suppression of the erased state threshold voltage drift (room temperature V/sub t/ drift) in cycled two-bit per cell silicon-oxide-nitride-oxide-silicon memory. Room temperature V/sub t/ drift is significantly decreased by using bottom oxide (BOX) with the thickness T/sub BOX/<50 /spl Aring/. Excellent retention properties are preserved for T/sub BOX/ up to 33 /spl Aring/. The results of single-cell studies were confirmed on 2 Mb memory arrays that underwent up to 1000 program/erase cycles. Peculiarities of hole injection into the nitride of oxide-nitride-oxide in the erase operation are considered for explanation of the observed results. The improvement is associated with a lesser amount of holes used in the erase.