A reconfigurable systolic architecture for UMTS/TDD joint detection real time computation

Multiuser detectors based on joint detection have been proposed to enhance the performance of the classical RAKE receiver in TD-CDMA systems. They significantly improve the performance of the RAKE receiver which suffers from multiple access interference. This is the case when non perfectly synchronised users are sharing the same frequency band at the same time (uplink case) or when they are experiencing multipath channels (downlink and uplink). These are classical conditions of mobile TD-CDMA communications as for instance in UMTS/TDD. The main drawback of joint detection algorithms is their computational complexity. There, the DSP approach shows its limit when multimedia compliant data rate must be addressed as is the case for UMTS/TDD and especially when long delay profile channels must be addressed. We propose a specific architecture that significantly improves the real-time system throughput with a reasonable hardware cost. This approach is based on an SIMD structure known as systolic array. The systolic array is a well known architecture mainly used for 1 dimensional or 2 dimensional signal processing. The architecture described in this paper is a derivation of the linear systolic array (Kung and Leiserson). The architecture is presented in this paper and we describe how the systolic array has been modified to address the zero-forcing joint detection algorithm in the UMTS/TDD context. We also describe how the algorithm can be simplified to lower the computation effort. Fixed-point accuracy degradation is discussed on an AWGN channel, and the hardware cost for an FPGA target is given.