JFET transistors for low-noise applications at low frequency

We describe a methodology to study and select JFET transistors, to be adopted for the readout of bolometric detectors, which makes use of a novel instrument capable of doing very accurate automatic noise measurements at low frequency. Clever design criteria and properly selected biasing conditions allow outstanding results in terms of noise and power dissipation. Noise was explored at very small power dissipation, 2.5 /spl mu/W, and JFET transistors were biased in a nonconventional region at low temperature.