A drain avalanche hot carrier lifetime model for n- and p-channel MOSFETs

A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as /spl tau/(I/sub d//W)/sup 2//spl prop/(I/sub sub//I/sub d/)/sup -m/. The formula is different from the conventional /spl tau/I/sub d//W-I/sub sub//I/sub d/ model in that the exponent of I/sub d//W is 2, which results from the assumed mechanism of the two-carrier recombination. It is shown that the mechanism gives a physical basis of the empirical /spl tau/-I/sub sub//W model for NMOSFETs. The proposed model has been validated experimentally both for NMOSFETs and for PMOSFETs. Model parameters extracted from experimental data show that carrier critical energies for creating damage are lower than the interface potential barriers. It is supposed that oxide band edge tailing enables low-energy carriers to create the damage. The channel hot electron condition becomes the worst case in short channel NMOSFETs, because gate voltage dependence of the maximum channel electric field decreases.