0.13-/spl mu/m RF CMOS and varactors performance optimization by multiple gate layouts

0.13-/spl mu/m radio frequency (RF) CMOS devices with multifinger gate structure have been fabricated by the standard logic process, and the measured effective gate-length is 80 nm. Extensive RF characterization has been done to obtain cutoff frequency (f/sub T/), associated power gain cutoff frequency (f/sub max/), minimum noise figure (NF/sub min/), output power (P/sub out/), and power added efficiency (PAE) for RF circuit design and to explore the optimized gate layout in terms of the extracted RF device parameters. Our important finding to be reported in this paper is that an optimized unit finger width (W/sub F/) exists by trade-off among f/sub T/, f/sub max/, NF/sub min/, P/sub out/, and PAE. Under fixed total width to achieve the same current drivability (I/sub ds/), the smaller W/sub F/ and the larger finger number (N/sub F/) leads to higher f/sub max/ but lower f/sub T/ due to trade-off between gate resistance (R/sub g/) and parasitic gate capacitance. As for NF/sub min/ complicated by f/sub T/ and R/sub g/, counter-balance between parasitic gate capacitance and R/sub g/ leads to nearly constant NF/sub min/ w.r.t. various splits of (W/sub F/,N/sub F/). Regarding P/sub out/ and PAE, W/sub F/ of 4 /spl mu/m and N/sub F/ of 18 is the optimized layout parameter, which offers the maximum P/sub out/ of around 11 dBm and PAE of 30.5% at 5.8 GHz. The performances of accumulation-mode MOS varactors with different gate layout structures are also investigated in this report. Since the same area varactors with different gate layout may result in different parasitic resistance and fringing capacitance, which will affect the capacitance tuning range and the associated Q-factor. The maximum Q-factor is about 59 of the 120 /spl mu/m/sup 2/ gate area varactor, and its tuning range is from 210 fF to 1.64 pF, where the maximum C/sub max//C/sub min/ ratio is about 7.8.