A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency

This study demonstrates for the first time the significant performance enhancement that calibration brings to folding-interpolating analog-to-digital converters (ADCs). The resulting 1.8-V ADC in 0.18-/spl mu/m CMOS achieves a conversion rate exceeding 1.6 GSample/s, since the amplifier device sizes can be minimized to maximize speed without the restriction of device matching. At 1.6 GS/s, the ADC achieves 0.15 LSB DNL, 0.35 LSB INL, 7.6 effective number of bits (ENOBs) at 100 MHz input, and 7.26 ENOB at Nyquist. At this speed, current consumption from a single 1.8-V supply is 245 mA analog, 185 mA digital, and 90 mA for the LVDS drivers. The ac performance is approximately 1.5 ENOBs higher compared to the same circuit with calibration disabled. The use of best design practices to optimize the ADC linearity prior to introducing calibration resulted in this small required dynamic calibration range, simplifying the calibrator circuitry and resulting in stable continuous performance over time without recalibration. Therefore, the fully on-chip calibration is performed automatically, just one time at power-up.