Generation of test patterns without prohibited pattern set

This work reports the design of a fool proof on-chip test pattern generator (TPG) for very large scale integration circuits. The TPG is designed to generate pseudorandom test patterns without a given prohibited pattern set (PPS). It ensures desired pseudorandom quality of the generated test patterns and maintains fault coverage close to the figures achieved with a conventional maximal length linear feedback shift register/cellular automaton (CA)-based TPG. The theory of vector subspace generated by a CA (Chaudhuri, 1997) has provided the foundation of this design. The proposed TPG does not incur any additional cost for the avoidance of PPS.