A weighted fair queuing finishing tag computation architecture and implementation

This paper investigates a customized implementation for Xilinx Virtex Pro board of a weighted fair queuing (WFQ) tag scheduler that has the capacity to serve 8,000 individual sessions at over 100MHz. The implementation is actually capable of handling up to 64,000 different sessions requiring only the use of a minimal size FPGA. This represents an excellent hardware cost for a next generation terabit router.