Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs

We present an analytical framework to identify the tradeoffs and performance impacts associated with different SoC platform configurations in the specific context of implementing multimedia applications. "Configurations" in this case might include sizes of different on-chip buffers and scheduling mechanisms (or associated parameters) implemented on the different processing elements of the platform. Identifying such tradeoffs is difficult because of the bursty nature of on-chip traffic arising out of multimedia processing and the high variability in their execution requirements, which result in a highly irregular design space. We show that this irregularity in the design space can be precisely captured using an abstraction called variability characterization curves.