Built-in self-test design of motion estimation computing array

This paper presents an implementation of built-in self-test (BIST) design of motion estimation (ME) computing array, which is the main part of MPEG-2 video encoder. The goal of the design is to offer high reliability for the coding system. Our design is carried out on gate level in both VHDL and Verilog HDL and then synthesized into FPGA. Design verification is also performed using logic simulation and fault simulation.