A normalized intrinsic delay model of static CMOS complex gates for deep submicron technologies

In this paper, we present a delay model that can estimate the normalized intrinsic delay of an arbitrary static complex CMOS gate (SCCG) based on topology and technology fitting parameters. Our approach is to convert the series-parallel connected MOS transistors into an equivalent RC circuit and calculates the normalized output intrinsic delay by an analytically derived formula. The accuracy of the model is evaluated for several complex gates in various deep submicron (DSM) technologies. The model showed a relatively good accuracy when compared with BSIM3V3 based Spectre simulation. The average error is around /spl plusmn/10% and the maximum error is close to /spl plusmn/13%. Our model contributes to library-free technology mapping.