A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process

A discrete-time sigma delta ADC is presented, that filters and decimates by two the input data samples, while providing amplification in its input sampling stage. This compact architecture allows operating preceding blocks at twice the ADC's clock frequency, thus improving the noise performance of the receive channel. The presented approach has been validated and incorporated in a commercial Bluetooth receiver IC, realized in a 1.5 V, 130 nm digital CMOS process.