An electrically robust method for placing power gating switches in voltage islands

Leakage power is quickly becoming a major design concern in modern VLSI chips. One design technique that allows the efficient control and reduction of leakage power involves using voltage islands which can be selectively turned on or off. Power gating switches are huge transistors which connect the voltage island and chip power grids. The power gating switches are turned off to disconnect the power supply from the voltage island when in "idle" or "sleep" state; thus reducing leakage power dissipation. In this paper, we present an efficient and automated algorithm for placing power gating switches in voltage islands so as to meet the electrical requirements of the design while guaranteeing the design specifications of the switches and minimizing their area overhead. Experimental results illustrate the efficiency of the proposed approach in determining an electrically robust placement of power gating switches.