Opportunities and challenges in asymmetric device implementation [CMOS device scaling]

Gate length (L/sub GATE/) scaling to reduce CMOS delay is becoming problematic due to high gate currents from thin gate dielectrics, process induced L/sub GATE/ variation, and high channel dopings that reduce carrier mobility. These issues have led to tailoring of transistor architecture components and a "multiple everything" approach (e.g. multiple oxides, multiple threshold voltages) for both digital and analog circuit elements. Higher mobility transistor structures are desirable because transistor delay can be reduced without the penalties of gate current or L/sub GATE/ variation. Individual tailoring of source and drain is an area where further gains can be realized, and is the subject of this work. Transistors with asymmetric halo have been developed and, for the first time to our knowledge, implemented in a highly complex, seventh generation microprocessor with >10/sup 7/ transistors. Opportunities and challenges for both digital and analog design with asymmetric transistors are explored.