An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter

This paper describes a low jitter phase-locked-loop (PLL) with a 4/sup th/ order control path, and a dual control voltage ring oscillator. Near constant voltage controlled oscillator (VCO) gain over process variations, in addition to compensation for feedback ratio variation, allows improved control of the PLL bandwidth. The PLL exhibits improved noise immunity with a wide (5:1) VCO frequency range, without the need for band switching or calibration routines. This PLL is fabricated in a 0.18 /spl mu/m CMOS logic process and exhibits <4 ps rms accumulated jitter.