Notice of Violation of IEEE Publication Principles: A 2-5GHz low jitter 0.13 μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]

Notice of Violation of IEEE Publication Principles

"A 2-5GHz low jitter 0.13 μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]"
by Maxim, A.
in the Proceedings of the IEEE 2004 Custom Integrated Circuits Conference,
3-6 Oct. 2004 Page(s): 147 - 150

After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.

Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.
A low-noise ring oscillator based PLL frequency synthesizer was realized for wideband tuner applications. The reference spurs are minimized using a fast reset, precharged phase-frequency-detector and a dynamic current matching charge-pump. The PLL has a single power supply, while a shunt regulator was used to bias the digital blocks without coupling noise to the analog supply. A two stage symmetric NFET load ring oscillator was used for both low phase noise and high frequency operation. A noise attenuating loop filter was implemented, that in conjunction with a Miller capacitance multiplication allows the on-chip integration of the loop filter capacitor.