Influence of metal gate materials and processing on planar CMOS device characteristics with high-k gate dielectrics

Scaled CMOS transistors with several types of metal gates on hafnium based high-k dielectrics were processed and studied to understand the influence of metal gates on device characteristics. The different metal gates that were comparatively studied include (a) TiN processed by ALD and PVD, and (b) PVD processed TaSiN and a multilayer HfN/Ta/TiN stack. From comprehensive electrical and nanostructural characterization, it was concluded that the differences in the properties of the devices, with ALD TiN gate electrodes compared to PVD TiN were due to the presence of the additional process grown interfacial oxide layer in the former samples. When comparing the TaSiN and multilayer HfN/Ta/TiN stacks, it was noted that the variation in device characteristics could be explained by the higher amount of nitrogen pile up at the high-k-Si interface for the multilayer metal stack. In all cases, the influence of processing on the nanostructure was addressed and a preliminary understanding of the processing-structure-property interrelationship is presented.