New power saving design method for CMOS flash ADC

A new power saving design method for CMOS flash ADC is presented. With an inverter as a comparator along with an NMOS and a PMOS as switches, we use bisection method to let only half of comparators in flash ADC working in every clock cycle. An example of 6-bit flash ADC operates at 200 MHz sampling rate and 3.3 V supply voltage is demonstrated. The power consumption of proposed circuit is only 40.75 mW with HSPICE simulation. Compared with the traditional flash ADC, our bisection method can reduce up to 43.18% in power consumption.