Design of a concurrent dual-band receiver front-end in 0.18 /spl mu/m CMOS for WLANs IEEE 802.11a/b/g applications

A fully monolithic dual-band concurrent receiver chip for IEEE 802.11a, 802.11b and 802.11g applications is presented in a 0.18-/spl mu/m CMOS 1P6M technology. A low IF architecture was chosen in order to achieve a low-cost and low-power solution with a high level of integration compared to direct conversion architecture. This mixer can operate as a sub-harmonic mixer and even as a traditional Gilbert mixer if LO ports connecting to each other to find two RF inputs and two LO inputs. For a 1.8 V power supply, the overall power consumptions are 84.3 mW, with 3.5 dB and 6.3 dB overall receive-chain noise figure for 2.45 GHz and 5.25 GHz, respectively.