Design techniques for CMOS very-low-voltage operational amplifiers with enhanced power supply rejection ratio

Two very-low-voltage operational amplifiers in standard 0.35 /spl mu/m CMOS process are presented. They have adopted folded-mirror active load and folded-cascode active load, respectively in the input stage, which save input swing. Cascode compensation offers a much improved high-frequency PSRR. Simulation results are provided and the corresponding performances are discussed and compared. Simulation results indicate that those circuits show superior power supply rejection at high frequencies.