A fully differential high-speed double-edge triggered flip-flop (DETFF)

A high-speed double-edge-triggered flip-flop designed in 0.18 /spl mu/m CMOS technology is presented. Flip-flops, to a large extent, determine the speed of synchronous systems. The proposed flip-flop can operate with a clock rate as high as 12.5 GHz, which translates to 25 Gb/s data rate. It samples the data on both edges of the clock. All signals are realized differentially. The differential output swing is 0.8 V with a 1.8 V power supply. The average power consumption is 7 mW. A performance comparison between the proposed flip-flop and a single-edge triggered flip-flop realized in the same technology is also presented.