Low-power design for real-time image segmentation LSI and compact digital CMOS implementation

We present a low-power design for real-time digital image segmentation LSI. We design the CMOS test-chip in a 0.35 /spl mu/m 2-Poly 3-Metal CMOS technology, based on a boundary active only architecture. The design area for 41 /spl times/ 31 pixels is 51.1mm/sup 2/ and the integration density is 26.5pixel/mm/sup 2/. From the circuit simulations at 3.3V supply voltage and 10MHz clock frequency, we obtain a power dissipation of 21.8mW and an image segmentation time of 23/spl mu/sec.