A 1.7/spl sim/3.125Gbps clock and data recovery circuit using a gated frequency detector

A fully integrated clock and data recovery (CDR) circuit with the proposed gated frequency detector (GFD) is presented. It has been realized in a standard 0.25-/spl mu/m CMOS technology. The proposed voltage-controlled oscillator (VCO) can achieve wide operation range and small K/sub VCO/ by employing the analog/digital dual loop architecture. It can relax the constraint on choosing the loop parameter to reduce the size of the on-chip capacitor. The proposed GFD will make the frequency lock time fixed and can avoid the harmonic locking problem for wide data rate operations. All measured BERs are less than 10/sup -12/ with the data rate from 1.7Gbps to 3.125Gbps.