Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems

This paper proposes an area-efficient architecture to implement the Modified Euclidean algorithm (MEA), which is frequently used in Reed-Solomon decoders. We present the new ME architecture to achieve high-throughput rate and reducing hardware complexity. We propose a folding architecture to reduce the hardware complexity about 50% compared to the fully parallel architecture. The Modified Euclidean algorithm has been implemented in 0.18-/spl mu/m CMOS technology with 1.8V supply voltage. The results show that total number of gates is about 20K and it has a data processing rate of 3.2Gbit/s at clock frequency of 400 MHz. The proposed area-efficient architecture can be readily applied to 10Gbase-LX4 optical communication systems.