New CML latch structure for high speed prescaler design

This paper emphasizes on the design and analysis of current mode logic latches and their application in a frequency prescaler. Operation of a conventional CML latch is analyzed and a clock feedback structure is proposed for increased stability with reduced delay parameters. A low power design technique is presented for current mode logic frequency prescalers, which allows the master and slave latches to be merged together so that they use a single current source. This significantly reduces the power consumption and area and also offers lower terminal capacitances resulting in faster circuit operation.