A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs

The conventional register-controlled delay locked loop (RCDLL) with a single delay line requires a complex logic circuit following the phase comparator to prevent the false lock. A RCDLL with two delay lines was published to reduce the chip area and power consumption by comparing the frequency-divided slow signals. Further reductions of 20% in both chip area and power consumptions were achieved in the RCDLL proposed in this work by using a single delay line. The duty cycle of the clock divider output was adaptively changed between 25% and 50% according to the external clock frequency to minimize the number of delay elements and hence the jitter of DLL output clock. The adaptive-change of duty cycle reduced the peak-to-peak jitter of data output from 800 ps to 400 ps at the data rate of 266 Mb/s in the production 256-Mb DDR SDRAM. The worst-case power consumption and the chip size of the RCDLL chip fabricated by using a 0.15-/spl mu/m CMOS technology were measured to be 12-mW and 0.16-mm/sup 2/, respectively, at the data rate of 400 Mb/s and the supply voltage of 2.5 V.