Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 /spl mu/m CMOS

This paper describes a 0.13 /spl mu/m CMOS, 8Gbps I/O receiver that uses on-die circuits for receiver adaptation and system characterization. On-die adaptive control is used to tune a 4-tap receive-side analog equalizer, cancel receiver offsets, and determine optimal sampling phase. Adaptive equalization improves data rates by 1.3/spl times/-2/spl times/ over 2"40" FR4 channels. Noise-margin degradation due to statistical variation in adapted coefficients and offsets is less than 3% of the signal swing. On-die circuits are also used to characterize link performance, channel response, and receiver circuits.