A circuit design based approach for 1/f-noise reduction in linear analog CMOS IC's

A new circuit design based approach for 1/f noise reduction in linear analog CMOS circuits is presented using a device physics based effect. Compared to a reference circuit, a threefold reduction (5 dB) at 10 Hz in 1/f noise is achieved for an operational amplifier designed in a standard 0.12 /spl mu/m, 1.5 V CMOS technology.