A pixel-parallel image processor for Gabor filtering based on merged analog/digital architecture

Gabor filtering is a powerful feature extraction method for image recognition. We propose a pixel-parallel processor for Gabor filtering using a newly developed algorithm with nearest-neighbor connections. The LSI has been designed using 0.35 /spl mu/m CMOS technology based on the merged analog/digital circuit architecture, which uses pulse-width modulation (PWM) signals. The LSI includes 62/spl times/71 pixel circuits on a 9.8 mm sq. chip area. Experiments using the fabricated LSI have verified that the spatial frequency of the image is correctly extracted.