A 4.8-ns random access 144-Mb twin-cell-memory fabricated using 0.11-/spl mu/m cost-effective DRAM technology

A 144-Mb twin-cell-memory was fabricated using 0.11-/spl mu/m cost-effective DRAM technology. A direct-sense-amp with a three-stage sensing scheme can achieve a random access time of 4.8 ns. The source-separated restore-sense-amp enables a random cycle time of 6.0 ns. The peak bandwidth is 48 Gb/s with separate I/O and simultaneous read/write operations. High performance was also realized using W/WNx dual-gate CMOS technology with a p+ gate memory-cell-transistor.