A CMOS 64MSps 20mA 0.85mm/sup 2/ baseband I/Q modulator performing 13 bits over 2MHz bandwidth

A CMOS 64MSps 2-1-1 cascaded /spl Sigma//spl Delta/ I/Q modulator optimized for WCDMA applications achieves more than 13 bits over 2MHz bandwidth. A new way for sizing cascaded /spl Sigma//spl Delta/ architectures based on comparator equivalent gain, and an improved dynamic element matching method resulted into an area and power efficient modulator design. The total consumption of two modulators plus built-in voltage and current reference generators is about 20mA at 2.7V. Total active area is 0.85mm/sup 2/ in a 0.35 /spl mu/m CMOS technology.