32 mW self contained OFDM receiver ASIC for mobile cellular applications

An OFDM receiver ASIC targeting cellular terminals has been designed and fabricated in 0.18 /spl mu/m CMOS. The receiver incorporates a front-end receiver, pre/post-FFT processing units, a 1024-point complex (I)FFT processor, a channel estimator and corrector, all digital synchronization loops, and a control and configuration interface. Low power circuit techniques and system algorithm optimization lead to the final receiver ASIC that dissipates only 32 mW while providing a (uncoded) date-rate of 8.192 Mb/s, making the chip suitable for packet-based mobile applications.