A /spl Sigma/-/spl Delta/ fractional-N synthesizer with a fully-integrated loop filter for a GSM/GPRS direct-conversion transceiver

This paper presents a fractional-N synthesizer with a 3-bit 4th-order interpolative /spl Sigma/-/spl Delta/ modulator for a GSM/GPRS direct conversion transceiver. With an integrated VCO and an integrated loop filter, the synthesizer achieves the phase noise performances less than -78dBc/Hz at close-in offset and less than -116dBc/Hz at 400kHz offset. The chip was fabricated and evaluated in a 0.35 /spl mu/m SiGe BiCMOS process.