A VLSI implementation of an adaptation algorithm for a pre-emphasis in a backplane transceiver

Two different hardware structures of a sign-sign block least-mean-square (LMS) algorithm for an adaptive pre-emphasis in a backplane transceiver have been implemented in Verilog targeting the TSMC 0.18 /spl mu/m CMOS technology. Functional models and Matlab code have been developed to simulate a transceiver system for both structures. A pulse amplitude modulated four-level (4-PAM) signaling technique is used in the Matlab simulation. Results show that the proposed parallel adaptation engine is four times faster than the published round-robin adaptation engine in terms of coefficient update rate with comparable hardware. Both circuits prove that digital CMOSP18 standard cells can be used directly to achieve 625 MHz timing constraints. A custom circuit is not needed to implement the digital adaptation algorithm for the analog adaptive pre-emphasis up to 625 MHz.