New latch-up failure mechanism between different power pins in the mixed-voltage process [CMOS ICs]

A new latch-up failure phenomenon, induced by the parasitic P-N-P-N path between different power pins, is reported here. The system voltage difference between IO and core blocks is the major factor to see whether the chips will have latch-up failure or not. This latch-up failure only occurs in 0.13 /spl mu/m and 0.18 /spl mu/m processes because the system voltage difference between IO and core circuitry could hold and sustain the latch-up path between IO and core power pins, but latch-up test passes in 0.25 /spl mu/m because the parasitic P-N-P-N path could not be turned on. A traditional latch-up protection methodology with guide-ring insertion works well here, and chip designers need to be aware of this phenomenon and follow the design guideline for IO and core circuitry before the chip is taped-out.