Modeling of wearout, leakage, and breakdown of gate dielectrics [MOSFET]

We present a set of models for the simulation of gate dielectric wearout, leakage, and breakdown. Wearout is caused by the leakage-induced creation of neutral defects at random positions in the dielectric layer, which, if occupied, degrade the threshold voltage of the device. Leakage is due to direct and trap-assisted tunneling through these defects. Finally, gate dielectric breakdown is triggered by the formation of a conductive path through the insulator. To allow the trap characterization, and for the simulation of fast transients, the modeling of trap charging and discharging processes is outlined. The model has been implemented into a 3D device simulator and is used for the characterization. of ZrO/sub 2/-based dielectrics and for the study of gate leakage and wearout effects in standard CMOS inverter circuits.