Applications of plan-view TEM analysis to IC debugging

In this report, applications of plan-view TEM analyses to IC debugging has been applied to some FA cases, where frequently used tools, such as SEM, FIB, AFM, etc., are not able to reveal the crystalline defects buried in the Si substrate. The novel examples include IC process induced oxidation stacking faults, sidewall profile of shallow trench isolation (STI), aggressive layout design induced active-to-active area breakdown, mask design error induced improper ion implantation, ESD failure induced local bum-out, and metal silicide encroachment.