Design considerations for DC SQUIDs fabricated in deep sub-micron technology

Practical SQUIDs with well-coupled input coils of usable inductance have generally been fabricated at the 2-5 mu m level of lithography. Other technologies, silicon in particular, are now routinely practised at the 0.5 mu m level of lithography with impressive demonstrations at the 0.1-0.25 mu m level not uncommon. The implications of applying such a fabrication capability to advance DC SQUID technology are explored. In particular, the issues of scaling practical DC SQUIDs down to the 0.1-0.25 mu m regime are examined, using as a prototype design the basic washer SQUID with a spiral input coil. A technical path is mapped out that leads to a practical SQUID less than 0.05 mm/sup 2/ in area with a tightly coupled 2- mu H input coil, user-friendly voltage-flux characteristics, minimal flux creep related hysteresis, and coupled energy sensitivity approaching the quantum limit at 4.2 K.