A 90nm dual-port SRAM with 2.04 /spl mu/m/sup 2/ 8T-thin cell using dynamically-controlled column bias scheme

A high-density dual-port SRAM (DP-SRAM) with a 2.04 /spl mu/m/sup 2/ cell size is implemented in 90 nm CMOS technology. A dynamically-controlled column-bias scheme is presented, which reduces the active power by 64% and the stand-by current by 93%.