40Gb/s amplifier and ESD protection circuit in 0.18/spl mu/m CMOS technology

A triple-resonance LC network increases the bandwidth of cascaded differential pairs by a factor of 2/spl radic/3, yielding a 40 Gb/s CMOS amplifier with a gain of 15 dB and a power dissipation of 190 mW from a 2.2 V supply. An ESD protection circuit employs negative capacitance along with T-coils and pn junctions to operate at 40 Gb/s while tolerating 700 V.