ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism

On-chip ESD (electrostatic discharging) protection is a challenging IC design problem. New CAD tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a smart parametric checking mechanism and the first intelligent CAD tool, entitled ESDInspector, developed for full-chip ESD protection circuitry design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35/spl mu/m BiCMOS.