VLSI architecture of the reconfigurable computing engine for digital signal processing applications

In this paper, a novel reconfigurable computing engine for digital signal processing applications is proposed. The kernel component of the reconfigurable computing (RC) engine is the general-purpose processing cluster (GPPC) array, which is constructed of the GPPCs, as an MIMD model to achieve high flexibility for mapping applications and algorithms to the RC engine. GPPC performs the data-parallelism operations efficiently using the SIMD instructions. Therefore, GPPC can not only execute the 32-bit operations but also perform 4-way 8-bit operations or 2-way 16-bit operations simultaneously. For the efficient connectivity, the inter-GPPC-row reconfigurable network is also proposed to achieve the requirements of high flexibility, low complexity, small area and short network delay.