High performance sense amplifier circuit for low power SRAM applications

A high performance sense amplifier (SA) circuit for low power SRAM applications is presented in this paper. The transistor stage number of the proposed SA from VDD to GND is reduced for fast low voltage operation. Thus the proposed sense amplifier which is implemented in 0.35 /spl mu/m CMOS process can work at 100 MHz with voltage as low as 1V. The improvement of sensing delay is 6-14% for various output loading. As the proposed SA works at 3.3 V, the simulations show that this design has 14% and 63% power delay product improvement over the prior art and conventional sense amplifier, respectively.