Data-retention flip-flops for power-down applications

A novel technique for retaining data in flip-flops in power-down applications is presented. In flip-flops data is stored in cross-coupled inverters. Cross-coupled inverters can hold their states in the power down mode, if their inputs are properly gated. Based on this fact, simple clock and data gating circuitries are employed in flip-flops to retain their data in the power-down mode without using any extra data-preserving latches. In a predictive 70 nm technology node, a transmission-gate flip-flop based on the proposed data-retention scheme exhibits 18X reduction in standby leakage compared to a conventional transmission-gate flip-flop. The proposed data-retention scheme also exhibits 40% area reduction compared to the conventional balloon scheme. A 16-bit shift-register using data-retention flip-flops has been successfully fabricated and tested in a 0.25 /spl mu/m CMOS process.