CMOS APS imager employing 3.3 V 12 bit 6.3 MS/s pipelined ADC

A novel 256/spl times/256 CMOS active pixel sensor (APS) system with 12 bit, 6.3 Msample/s (MS/s) CMOS pipelined analog to digital converter (ADC) integrated on chip is presented. The test chip has been implemented in 0.35 /spl mu/m 2P4M process, operated by a 3.3 V supply and is expected to dissipate 55 mW. The total area of the prototype is 12 mm/sup 2/, and the core area of ADC is 18% from the total area. System architecture and operation are discussed and simulation results are presented.