The design of a differential CMOS charge pump for high performance phase-locked loops

The design methodology and the test results of a low-voltage differential charge pump structure for phase-locked loop (PLL) applications are presented. The structure is composed of two charge/discharge blocks, a replica bias circuit, and a sampled data common-mode feedback (CMFB) block that adjusts the pump-up current for symmetrical differential outputs and a wider output voltage range. A prototype is fabricated using a 0.18 /spl mu/m n-well CMOS technology to test the charge pump in a high performance PLL, running internally at 2.5 GHz with -123 dBc/Hz phase noise at 1 MHz frequency offset.