Low complexity System-on-Chip architectures of Parallel-Residue-Compensation in CDMA systems

In this paper, we propose a novel multi-stage Parallel-Residue-Compensation (PRC) receiver architecture for enhanced suppression of the MAI in CDMA systems. We extract the commonality to avoid direct Interference Cancellation and reduce the algorithm complexity from O(K/sup 2/N) to O(KN). In the second part, scalable VLSI architectures are implemented in an FPGA prototyping system with an efficient Precision-C based System-on-Chip (SOC) design methodology. The design of Sum-Sub-MUX Unit (SMU) combinational logic avoids the usage of dedicated multipliers with at least 10 X saving in hardware resources. The most area/timing efficient design only uses areas similar to the most area-constrained architecture but gives at least 4 X speedup over a conventional design.